Prof. Davide Zoni
Tenure-Track Assistant Professor (RTDB)
| Office: | Building 20, First Floor, Room 002 | |
| DEIB, Politecnico di Milano, | ||
| via Ponzio 34/5, 20133 Milano, Italy | ||
| Phone: | 02 2399 3496 (office), | |
| 02 2399 9613 (lab) | ||
| Email: | davide[dot]zoni[at]polimi[dot]it |
Curriculum Vitae
About me
Welcome to my personal homepage at Politecnico di Milano. Here you can find information related to my research, teaching, and technology transfer activities, as well as the theses available for MSc and PhD students.
I am an Assistant Professor (RTDB) at the Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB) of Politecnico di Milano, where I received an MSc in Computer Engineering in 2010, and a PhD in Information Technology in 2014. I am also part of HEAPlab and the Computing Systems Architecture group at DEIB.
My teaching activities are related to computer science and engineering courses held at both Politecnico di Milano and Università degli Studi di Parma with emphasis on hardware design and computer architectures.
My research interests target the design and verification methodologies for digital computing platforms at the edge, focusing on low-power single- and multi-cores, hardware design for deep learning, and hardware security.
I am also the co-founder and CEO at Blue Signals Srl, an innovative startup and spin-off of Politecnico di Milano. Blue Signals develops technologies to support the design and implementation of edge devices secure against implementation attacks, comprising both fault and side-channel attacks.
Research
My research interests target the design and verification methodologies for digital computing platforms at-the-edge, with emphasis on low-power architectures, hardware security, and hardware support to deep learning. In particular, my research can be seen as organized in three branches that remain tightly connected due to the cross-related knowledge required in each of them.
Design of single- and multi-cores at the edge
In the current digital world, the hardware accelerators represent the de-facto solution to support the execution of compute-intensive tasks in edge devices efficiently. However, the design of the single- and multi-core processing elements and the system on a chip (SoC) where the accelerators are integrated is critical to the success of the overall computing platform. Indeed, hardware accelerators ensure an efficient computation only if they are integrated within an efficient computing platform. To this end, the design of efficient RISC CPUs, memories, and on-chip interconnects are all critical research areas. My research focuses on the hardware design of single- and multi-core platforms at the edge, carefully considering the low-power requirements, the cache hierarchy and coherence, and on-chip interconnects that may be point-to-point or bus-based architectures.
Hardware design for deep learning
The continuous improvement of current computing platforms fuels the tremendous success of machine learning and deep learning. The training and inference processes for any deep neural network strongly leverage the computational capability of the hardware platform and are far from efficient. However, and according to IEEE, deep-learning models are usually over-parametrized. Their training and inference costs in consumed energy and generated CO2 are reaching a critical break-even point. To this end, the research must deliver novel computing solutions to better support deep-learning solutions. My research focuses on the design of efficient deep-learning hardware accelerators.
Hardware security for IoT and devices at the edge
The IoT revolution shaped a tightly interconnected digital world made of billions of smart devices physically spread in the environment that are constantly digitizing, processing, and transmitting streams of data, some of which are sensitive, private, or critical. The possibility for the attacker to seize such smart devices enables the so-called implementation attacks that represent a new class of cyberattacks. Such attacks can be efficiently faced at the hardware level, thus imposing the employment of novel hardware design methodologies that include security as a standard design metric on par with the traditional power, area, and performance metrics. My research aims to design secure computing platforms and develop EDA tools to support the security analysis against implementation attacks.
Teaching
I teach several courses related to computer science and engineering
at both Politecnico di Milano and Università degli Studi di Parma.
The teaching material for courses held at Politecnico di Milano is available on the
WeBeep platform.
The teaching material for courses held at Università degli Studi di Parma is available on the
Elly platform.
Current teaching activities
Fondamenti di Informatica (6 CFU - First semester) BSc in Ingegneria Edile e delle Costruzioni, Politecnico di Milano
Embedded Systems (6 CFU - Second semester) MSc in Ingegneria Informatica, Università degli Studi di Parma
Architetture dei Calcolatori e Sistemi Operativi (ACSO) (10 CFU - First semester - teaching assistant) BSc in Ingegneria Informatica, Politecnico di Milano
Embedded Systems (5 CFU - First semester- teaching assistant) MSc in Ingegneria Informatica, Politecnico di Milano
Past teaching activities in the last three academic years
Fondamenti di informatica (6 CFU - since 2020) BSc in Ingegneria Edile e delle Costruzioni, Politecnico di Milano
Embedded Systems (6 CFU - since 2019) MSc in Ingegneria Informatica, Università degli Studi di Parma
Architetture dei Calcolatori e Sistemi Operativi (ACSO) (10 CFU - since 2018 - teaching assistant) BSc in Ingegneria Informatica, Politecnico di Milano
Digital Design for Embedded Systems (5 CFU - 2019) PhD course, Università degli Studi di Parma
Digital Design of Embedded Systems in the IoT and RISC-V Open Core Era (5 CFU - 2020) PhD course, Politecnico di Milano
Other ongoing teaching activities
Industrial courses on advanced topics in hardware design and verification (5 CFU-equivalent) Cefriel
Data analysis and visualization using Python (3 CFU) Passion in action, Ingegneria Edile e delle Costruzioni, Politecnico di Milano
Theses proposals
Thesis proposals to be carried out at HEAPlab and/or in collaboration with other research groups at DEIB and external companies are listed below. Links to useful information are provided for each thesis proposal. You may contact me by e-mail for further discussion.
FPGA-based implementation of lattice-based post-quantum cryptosystems
Quantum computing is expected to break the traditional public-key cryptography solutions in the next decades,
making it paramount to design new security solutions that can also resist attacks carried out by quantum computers.
Post-quantum cryptography (PQC)
aims to design cryptoschemes that can be deployed on traditional computers and that can resist against
both traditional and quantum attacks.
The deployed PQC solutions will have to satisfy not only security requirements, but also performance ones.
Providing
an
effective
hardware
support
is paramount to ensuring a wide adoption of post-quantum security solutions across scenarios ranging from HPC to edge devices.
CRYSTALS-Kyber and
CRYSTALS-Dilithium are
lattice-based PQC cryptoschemes accepted for standardization by USA's NIST,
both part of the same CRYSTALS (Cryptographic Suite for Algebraic Lattices) family and based on hard problems over module lattices.
The thesis foresees designing a hardware accelerator targeting FPGAs to support the CRYSTALS-Kyber key encapsulation mechanism and the CRYSTALS-Dilithium digital signature scheme in a single RTL design.
Tags: hardware design, post-quantum cryptography, lattice-based cryptography, hardware acceleration, FPGA
Hardware design of a superscalar and/or out-of-order CPU on FPGA targets
Superscalar processors can concurrently execute multiple instructions, i.e.,
they can simultaneously dispatch multiple instructions to different execution units,
thus implementing instruction-level parallelism within a single processor.
Out-of-order processors can execute instructions out of the original order,
looking ahead across many instructions to issue independent ones as fast as possible while
satisfying the dependencies and thus guaranteeing that the program produces the expected result.
The thesis foresees designing a superscalar and/or out-of-order CPU for FPGA targets, starting from an existing FPGA design of a single-core, in-order RISC-V CPU.
Tags: hardware design, CPU, superscalar, out-of-order, FPGA, RISC-V
Design of hardware cache coherence on multiprocessor SoCs on FPGA
Cache coherence is the uniformity of shared resource data stored in multiple local caches. When multiple processors in a multiprocessor system maintain caches of a shared memory resource, problems may arise with incoherent data.
The thesis foresees integrating a set of already-developed cores within a multiprocessor system on an FPGA target and developing a hardware mechanism for maintaining cache coherence within the multiprocessor, leveraging existing CPU and SoC developed in-house.
Tags: hardware design, CPU, cache coherence, FPGA, RISC-V
ML-driven exploration of synthesis and place-and-route directives of commercial EDA tools
Synthesis is a process by which a register transfer level (RTL) description of the desired circuit behavior, specified
in a hardware description language (HDL), e.g., Verilog and VHDL, is turned into a design netlist in terms of logic gates.
Place-and-route consists in placing all the logic elements within the resources available on the FPGA (placement)
and then connecting the placed components through the wires (routing).
The available commercial electronic design automation (EDA) tools provide an extensive set of directives to optimize
different aspects of the hardware design, such as resources utilization, power consumption, and timing,
within both the synthesis and place-and-route processes.
The thesis foresees exploring the different synthesis and place-and-route directives of a commercial EDA tool (Xilinx Vivado) and evaluating their impact on the hardware quality metrics when applied to a variety of IP components, such as CPUs, hardware accelerators, and HLS-designed cores, on a Xilinx FPGA target. The exploration will be driven by exploiting machine learning (ML) techniques.
Tags: electronic design automation, synthesis, place-and-route, machine learning, FPGA
Technology transfer
Technology transfer represents a critical activity in my professional career since it sustains the adoption in the real world of the most promising technologies developed within academia. Research per se is just research. I strongly believe that through technology transfer we can really impact the well-being and the quality of life of the whole society.